1. Field of the Invention
The invention relates to a semiconductor device, and relates particularly to a write-in/erase circuit of an electronically rewritable non-volatile semiconductor memory device (EEPROM) such as a flash memory, and a method thereof.
2. Description of Related Art
It is known in the art that a highly integrated NAND type non-volatile semiconductor memory device may be constructed by connecting a plurality of memory cell transistors (referred to as “memory cell” below) in series between bit lines and source lines to form a NAND string (for example, refer to Patent Document 1).
FIG. 1 is a block diagram illustrating an overall construction of a NAND type flash EEPROM relating to conventional example. FIG. 2 is a circuit diagram illustrating a construction of a memory cell array 10 of FIG. 1 and the peripheral circuit thereof.
Referring to FIG. 1, a NAND type flash EEPROM relating to a conventional example includes a memory cell array 10, a control circuit 11 for controlling the operation thereof, a row decoder 12, a high voltage generating circuit 13, a page buffer circuit 14 including a data rewriting and reading-out circuit, a column decoder 15, a command register 17, an address register 18, an operation logic controller 19, a status register 20, a Ready/Busy-bar (RY/BY) output terminal 53, a data input/output buffer 50 and a data input/output terminal 51.
In the memory cell array 10, a NAND cell unit NU (NU0, NU1, . . . ) is constructed by, for example, connecting 16 stack-gate structured electrically rewritable non-volatile memory cells MC0˜MC15 in series, as shown in FIG. 2. The drain end of each NAND cell unit NU is connected to a bit line BL through a selective gate transistor SG1 and the source end of each NAND cell unit NU is connected to a common source line CELSRC through a selective gate transistor SG2. The control gates of the memory cells MC arranged in row directions are coupled to a common word line, and the gate electrodes of the selective transistor SG1, SG2 are connected to the selective gate lines SGD, SGS arranged parallel to the word lines WL. One page, which is a write-in or readout unit, is a range of the memory cell selected by one word line WL. One block, which is a data erasing unit, is a range of a plurality of NAND cell units NU of one page or its integer multiples. In order for performing rewriting and reading of the data of the page unit, the page buffer circuit 14 includes a sense amplifier circuit (SA) and a latch circuit (DL) in each bit line.
The memory cell array 10 of FIG. 2 has a simplified structure, however, in which it can have a structure wherein a plurality of bit lines can share a page buffer. In this case, when writing in or reading out data, the number of bit lines which are selectively connected to the page buffer is a one page unit. FIG. 2 shows the range of the cell array within which data is inputted or outputted by one data input/output terminal 51. In order to select the word line WL of the memory cell array 10 and the bit line BL, the row decoder 12 and the column decode 15 are respectively arranged. The control circuit 11 carries out sequence control of data writing, erasing, and reading. The high voltage generating circuit 13 which is controlled by the control circuit generates a high voltage or a middle voltage used for data writing, erasing, and reading. The status register 20 controlled by the control circuit 11 stores pass/fail information of program or erase just finished and the status of the chip during programming, erasing and reading or not. And the status output from the Ready/Busy-bar (RY/BY) terminal 53 as: high is ready to next operation, and low is busy to do current operation.
The input/output buffer 50 is used to input/output data and input address signals. Specifically, data is transmitted between the input/output terminal 51 and the page buffer 14 through the input/output buffer 50 and the data line 52. The address signals inputted from the input/output terminal 51 are stored in the address register 18 and sent to the row decoder 12 and the column decoder 15 for decoding. The action control command is also inputted from the input/output terminal 51. The inputted command is decoded and stored in the command register 17 such that the command controls the control circuit 11. The external control signals, such as chip enable signals CEB, command latch enable signals CLE, address latch enable signals ALE, write-in enable signals WEB, readout enable signals REB, and so on, are brought into the operation logic controller 19. Thus, the inner control signals are generated corresponding to an action mode. The inner control signals are used to control data latching or transmitting processes on the input/output buffer 50, and further transmitted to the control circuit 11 for action controlling.
The page buffer 14 has two latch circuits 14a, 14b for multi-valued action or cache functions which are executed by switching. Specifically, when one memory cell memorizes a two value data of one bit, a cache function is provided. When one memory cell memorizes a four value data of two bits, a multi-value function is provided or a cache function still is effective even though the cache function is limited by address.